A three-dimensional integrated circuit (3DIC) is a multi-die integrated circuit manufactured by stacking silicon wafers and/or dies and interconnecting the dies vertically with vertical interconnections (VI). 3DIC typically provides reduction of wirelength and footprint compared to conventional 2D integrated circuits. A 2.5D IC is a multi-die horizontally tiled integrated circuit that uses VI to connect to a metallization layer for die-to-die connections. 2.5D ICs can provide capacity, performance, system space and overall system power consumption improvements compared traditional single die ICs.
3DIC and 2.5D IC are of therefore of great interest for cost and density scaling, as well as performance improvements. Mix-and-match die integration is an integration strategy that stacks or tiles slow (or smaller leakage) dies with fast (or more leakage) dies to improve parametric yield. Conventional approaches design each of the stacked or tiled dies independently. Thus, there is no holistic design achieved for the eventual stacking or tiling of any of the die.
Examples of these types of methods for mix-and-match die integration have been the subject of many publications. Ferri et al. [C. Ferri, S. Reda and R. I. Bahar, “Parametric Yield Management for 3D ICs: Models and Strategies for Improvement”, ACM JETCS 4(4) (2008), pp. 19:1-19:22] propose methodologies to benefit from the flexibility of die-to-die and/or die-to-wafer 3D integration with awareness of the inter-die process variation. Their optimization is reported to improve performance and parametric yield of 3DICs with one CPU die and one L2 cache die. Garg et al. [S. Garg and D. Marculescu, “Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits”, IEEE TVLSI 21(10) (2013), pp. 1903-1914] describe mathematical programs to improve the performance yield of 3DICs via mix and-match die integration. Chan et al. [T.-B. Chan, A. B Kahng and J. Li, “Reliability-Constrained Die Stacking Order in 3DICs under Manufacturing Variability”, Proc. ISQED, 2013, pp. 16-23] propose an integer linear programming-based method as well as a heuristic method to optimize reliability of 3DICs (i.e., to improve the mean time to failure).
To avoid the large runtime of thermal simulation, Juan et al. [D.-C. Juan, S. Garg and D. Marculescu, “Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors”, ACM TODAES 19(4) (2014), pp. 39:1-39:23] describes a learning-based model for temperature prediction in 3DICs. Based on the model, thermal-aware matching and stacking of dies is conducted to improve thermal yield.
Li et al [Z. Li, X. Hong, Q. Zhou, Y. Cai, J. Bian, H. H. Yang, V. Pitchumani, C.-K. Cheng, “Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization”, IEEE Trans Circuits Syst I 53(12) (2006), pp. 2637-2646] use a simulated annealing engine to partition blocks across tiers during the floorplanning stage to minimize wirelength. Others have cast 3D partitioning as a form of standard hypergraph partitioning. Thorolfsson et al. [T. Thorolfsson, G. Luo, J. Cong and P. D. Franzon, “Logic-on-logic 3D Integration and Placement”, Proc. 3D Systems Integration Conference, 2010, pp. 1-4.] use hMetis to partition the design into balanced halves while minimizing the number of cuts. A multilevel partitioning methodology is proposed in [Y. C. Hu, Y. L. Chung and M. C. Chi, “A Multilevel Multilayer Partitioning Algorithm for Three Dimensional Integrated Circuits”, Proc. ISQED, 2010, pp. 483-487], which first applies Hyperedge Coarsening (HEC) techniques to coarsen the netlist, then performs an FM-like K-way partitioning procedure to partition the netlist such that the number of VIs is minimized. An integer linear programming for 3D partitioning is formulated in [I. H.-R. Jiang, “Generic Integer Linear Programming Formulation for 3D IC Partitioning”, Proc. IEEE ISOCC, 2009. pp. 321-324], where the objective is to reduce the number of VIs subject to area balancing constraints.
Partitioning methodologies based on an initial 2D implementation solution have also been proposed. Cong et al. [J. Cong, G. Luo, J. Wei and Y. Zhang, “Thermal-Aware 3D IC Placement Via Transformation”, Proc. ASP-DAC, 2007, pp. 780-785] assign cells to tiers through folding-based transformations of an initial 2D placement solution. Based on a 2D implementation solution with scaled dimension (i.e., 0.7×), Path overall routing overflow; this can mitigate routing congestion and help overall routing overflow. This can also mitigate routing congestion and help minimize wirelength.
These prior optimization approaches operate at die level or wafer level (essentially, post-manufacturing). None of these methods address design-stage optimization and signoff for mix-and-match die integration. There are no techniques or system provided in these prior publications for optimization at time of design compilation. None of these works integrate mix-and-match die integration into design compilation.
The Fiduccia-Mattheyses (FM) optimization is a hypergraph partitioning heuristic that has been used in the context of VLSI design to conduct netlist partitioning in design optimizers. See, e.g., Caldwell et al., “Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning,” Proceedings ALENEX '99 Selected papers from the International Workshop on Algorithm Engineering and Experimentation, pp. 177-193 (Jan. 15-16, 1999). One example FM technique minimizes the number of cuts during design compilation. G. Karypis and V. Kumar, “Multilevel K-Way Hypergraph Partitioning”, Proc. DAC, 1999, pp. 343-348. Another technique minimizes the number of paths passing across different partitions. See, See, A. B. Kahng and X. Xu, “Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in Performance-Driven Bipartitioning”, Proc. ISPD, 2003, pp. 81-86. Such prior techniques fail to directly address timing slack or use a priori knowledge of mix-and-match constraints in 3D designs. Typical prior techniques only minimize the number of cuts (or vertical interconnects) between dies and are not aware of the mix-and-match context for timing analysis.